Fig 1. As an example of today’s ASIC design complexity, IBM’s Cu-32 ASIC product offering delivers 2.9K raw gates per square millimeter. Such advanced process nodes enable SoC design teams to ...
September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results