EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
Semiconductor Engineering

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...
EDN

Monterey integrates planner into physical design flow

SAN MATEO, Calif. — Monterey Design Systems Inc. has upgraded its IC Wizard hierarchical design planning tool to more effectively drive the company's System-Driven Physical Design (SDPD) solution.
Design-Reuse

AI in VLSI Physical Design: Opportunities and Challenges

As semiconductor technology pushes the boundaries of scale and complexity, traditional VLSI physical design methodologies are struggling to keep pace. The rise of Artificial Intelligence (AI), ...