As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s ...

This particular timing circuit can be used to time one-shot events from a few seconds to a few hours. And in standby mode (ie, with RLY1 and LED1 off), its power consumption is very low. This ...

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...