Semiconductor Engineering

Quality time?

System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional ...
EDN

Spotty support stymies broader acceptance of System Verilog, users say

SAN FRANCISCO — A handful of chip and systems companies said they are seeing real benefits from experiments and limited adoption of System Verilog, mainly in back-end design areas such as verification ...
Design-Reuse

Using Tcl to create a virtual component in Verilog

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...
Business Insider

Compound Photonics Selects Velocity CAE Design-to-Test Tools From Alliance ATE

SANTA CLARA, CA, Nov. 05, 2019 (GLOBE NEWSWIRE) -- via NEWMEDIAWIRE -- Alliance ATE Consulting Group, Inc. announces today that Compound Photonics U.S. Corporation, a global leader and innovator of ...